Erik Pardijs: Finite bases in the linear time-branching time spectrum with sequential composition and succesful termination
The process algebra TSP extends the process algebra BCCSP with sequential composition and successful termination. For BCCSP it is known, for all semantics in Van Glabbeek’s linear time-branching time spectrum of behavioural semantics, whether a finite basis exists. In this thesis, we study whether these semantics are finitely based over TSP. We discovered that none …continue reading
Mark Bouwman: A model-based test platform for rail signalling systems
As technology progresses, newer, and more complex, solutions are employed to verify that rail signalling systems are safe. Formal methods provide ways to increase rigour in the verification process. This precision, accompanied by the ongoing increase of computational power of computers, also opens up ways to partially automate parts of the verification process. We present …continue reading
Joel Garcia: Behavioural modelling of a wafer transport unit using mCRL2
As a master’s student I’m doing an internship with the assignement to design a model for an ASML wafer transport unit. The objective is to model the behaviour of two stages of the wafer transport unit: the wafer hanlder and the wafer stage. The model of such a machine is built by using the mCRL2 …continue reading
Jan Friso Groote: An attempt to reap the benefits of processor arithmetic without loosing the advantages of the numbers represented as rewrite systems
In mCRL2 numbers are represented using rewrite systems. The representation is based on binary operations. This is relatively concise but far less efficient than 64 bits operations on numbers available in processors. I will explain ongoing work towards an attempt to reap the benefits of processor arithmetic without loosing the advantages of the numbers represented …continue reading
Ruud van Vijfeijken: Performance evaluation of network on chip using formal models
Because of the increase in complexity of System-on-Chip (SoC) networks by using Network-on-Chip (NoC), latency has become a major issue in the design and validation. There are formal and mathematical methods to determine latency bounds of a NoC, such as network calculus, and low level simulation environments, such as a cycle-accurate simulation of the Register …continue reading
Olav Bunte: Quantitative model checking on probabilistic systems using plmu*+
Although most model checking logics focus on proving qualitative properties, with the logic plmu*+ introduced in Mio’s PhD thesis one can check the probability that some behaviour happens. In this work we try to bring this logic to practice. We attempt to find intuitive meaning for plmu*+-formulas with the aim to create guidelines to create …continue reading