The FSA group is part of the Model-Driven Software Engineering section of the department of Mathematics and Computer Science of the Eindhoven University of Technology. Research in the FSA group focusses on theories, techniques and tools for modelling and analysing the behaviours of (concurrent) systems. Among others, we study process algebras, semantics, model checking, logics, rewriting and satisfiability solving.
Application areas include protocols, hardware designs and industrial control systems. Examples include the verification of the control systems of the four large experiments in the Large Hadron Collider at CERN; analysis of networks-on-chips; formalisation of the industrial modelling and code generation language Dezyne; the analysis of the software architecture of the winning Stella Solar Car.
Tools developed by the group include mCRL2 (/ˈmak(ə)r(ə)l 2/) and MaDL. mCRL2 is a process-algebraic language with an award winning tool set for modelling and analysing concurrent systems. MaDL is a language with associated verification techniques for micro-architectures. The techniques focus on scalable liveness verification.
- FormaSig: Formal Methods in Railway Signalling Infrastructure Standardisation Projects (joint project with DB Netze A.G., ProRail, and the University of Twente; fully funded by DB Netze A.G. and ProRail)
- VOICE-B: Verification of OIL Interfaces and Components for Engineers (funded by Océ-Technologies B.V.)
- AVVA: Accelerated Verification and Verification Accelerated (NWO TOP grant)
- ASOME² (TU/e and ASML, IMPULS II)
- MERITS: Model extraction for re-engineering traditional software (NWO Big Software, with Philips Healthcare)
- VICTORIA: Verification In the Cloud TO Radically Improve Analyses (EU-FP7)
- Formal verification of cache coherent multi-core architectures (NWO TOP grant)
- DEWI: Dependable Embedded Wireless Infrastructure (Artemis project)
- ELVeN: Effective Layered Verification of Networks-on-Chips (NWO Open Competition)
- EURO-MILS: Secure European virtualisation for trustworthy applications in critical domains (EU-FP7)
- VOCHS: Verification of Complex Hierarchical Systems (NWO Open Competition)
- Allegio: All lifecycles and legacy entities guaranteed in operation! (NWO Commit)
- Functional Correctness of Communication Fabrics (Intel Corporation)
- Verified: Verified, Economical and Robust Integrated Functionality for In-vehicle Embedded Development (Senter-Novem)
- FVDAM: Formal Verification of Deadlock Avoidance Mechanisms (NWO Open Competition)
- VALICHIP: Validatie van cell-libraries en IP in chip design (Point One, with Fenix and NXP)
- TWINS: Optimizing HW-SW Co-design flow for software intensive system development (ITEA)
- COMFORTS: A Common Framework for Reactive and Timed Systems (NWO BRICS-FOCUS)
The paper “Formal Modelling and Verification of an Interlocking using mCRL2” by Mark Bouwman, Bob Janssen, and Bas Luttik has been accepted for presentation at FMICS 2019 in Amsterdam, The Netherlands.
The paper “Verification of Hypertorus Communication Grids by Infinite Petri Nets and Process Algebra” by Zaitsev, Shmeleva and Groote has been published in IEEE/CAA Automata Sinica. The paper explains how communication grids in the form …continue reading
The paper “Sequencing and Intermediate Acceptance: Axiomatisation and Decidability of Bisimilarity” by Astrid Belder, Bas Luttik and Jos Baeten has been accepted for presentation at CALCO 2019 in London, UK.
The paper “Correct and Efficient Antichain Algorithms for Refinement Checking” by Maurice Laveaux, Jan Friso Groote and Tim Willemse has been accepted for publication at FORTE 2019 in Lyngby, Denmark.
Mark Bouwman started as a PhD candidate on the FormaSig project in our group. The FormaSig project, led by Bas Luttik (TU/e) and Maarten van der Werff (ProRail), is a joint research project of DB …continue reading